Gate computer science questions with answers
GATE 2011,GATE free solved sample placement paper -of CSE,EEE,ECE
1 Consider an instruction pipeline with four stages (S1,S2,S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.
What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?
(a) 4.0
(b) 2.5 (Ans)
(c) 1.1
(d) 3.0
Speed up = (5+6+11+8)*1/(11+1) =30/12 = 2.5
2 An 8 kbyte direct mapped write-back cache is organized as multiple blocks, each of size 32 byte. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following
1 Valid bit
1 Modified bit
